1. Field of the Invention
The present invention relates to a digital signal reproducing circuit for reproducing a digital signal recorded on a magnetic tape, in particular, to such digital signal reproducing circuit using Viterbi code.
2. Description of the Prior Art
In a digital magnetic recording/reproducing apparatus as in a digital VTR, an equalizer is used to increase recording density and decrease error rate. In addition, construction which automatically and optimally controls the charactersitics of an equalizer is known. Moreover, another decoding technique has been proposed. In this technique, intersymbol interference and non-linear distortion are expressed by automaton. The resultant data is decoded by applying the Viterbi algorithm. This technique is superior to conventional bit-wise determination technique.
FIG. 1 is a block diagram showing the construction of an example of a digital VTR reproducing circuit having a conventional automatic equalizer. In this circuit, a signal reproduced by a reproducing head 41 is sent to an equalizer 43 through a reproducing amplifier 42. The output signal of the equalizer 43 is sent to a channel decoder 44 which decodes a channel-encoded signal. The output signal of the channel decoder 44 is sent to an error correcting circuit 45 which decodes error-correction code. The resultant error corrected data is sent to a deshuffling/concealment circuit 46. The deshuffling process is the reverse process of the shuffling process which is performed on the recording side. Thus, the data sequence is restored to the original sequence. The error concealment process conceals error data, which has not been corrected by the error correction code, with correct data around the error data. The output data of the deshuffling/concealment circuit 46 is sent to a D/A converter 47 which converts the digital signal into an analog signal. The analog signal is obtained from an output terminal 48.
In the above-described digital VTR reproducing circuit, the error correcting circuit 45 detects an error of reproduced data and generates an error flag which represents whether or not such an error is present. Using this error flag, the error correction is performed. The error flag signal is sent to an arithmetic control circuit 49. A reset or enable signal or enable signal received from a terminal 50 is sent to the arithmetic control circuit 49. The arithmetic control circuit 49 calculates an error rate in a predetermined period (for example, an error rate per track of the magnetic tape). Thereby, a control signal which causes the error rate to be minimized is generated. With the control signal, gain characteristics and phase characteristics of the equalizer are controlled.
In the conventional construction, to accomplish highly accurate control, the error rate should be accurately detected. Thus, many data are required, thereby lowering response of the control. For example, it is experimentally known that to have an accuracy on the order of 2.times.10.sup.-6 of error rate, reproduced data of 10 tracks is required. In addition, the error rate tends to be adversely affected by a drop-out. Thus, even if the amount of data for detecting the error rate is increased, the controling accuracy of the equalizer is not proportionally improved.